The present invention relates to Electrical Over-Stress ("EOS") and Electrostatic Discharge ("ESD") protection in high density integrated circuits.
Modern integrated circuits are easily damaged by excess voltages, and one common source of such potentially damaging voltages is caused when two materials are rubbed together. A person can develop very high static voltage, from a few hundred to several thousand volts, simply by walking across a room or by removing an IC from its plastic package, even when careful handling procedures are followed. The impact of ESD damage due to handling and testing can have a significant influence on product yield. Large ICs manufactured in advanced processes may only have 30 to 40 chips per six inch wafer. Any product loss due to ESD damage has a direct impact on profitability and even fall-outs of the order of 1% are not acceptable. Another issue which gives increasing importance to ESD control is the move toward replaceable ICs in electronic systems. Instead of replacing the whole circuit board, as used to be the standard practice, users are now encouraged to purchase upgrades to their microprocessors and memory cards and perform the installation themselves. Since the installation does not necessarily take place in an ESD-safe environment, the ICs need to be ESD robust.
A longstanding problem is that if such a high voltage is accidentally applied to the pins of an IC package, the discharge can cause gate oxide breakdown of the devices to which it is applied. The breakdown may cause immediate destruction of the device, or it may weaken the oxide enough such that failure may occur early in the operating life of the device and thereby cause later device failure in the field.
In MOS integrated circuits, the inputs are normally connected to drive the gate of one or more MOS transistors. (The term "MOS" is used in this application, as is now conventional, to refer to any insulated-gate-field-effect-transistor, or to integrated circuits which include such transistors.) Furthermore, all pins are provided with protective circuits to prevent voltages from damaging the MOS gates. These protective circuits, normally placed between the input and output pads on a chip and the transistor gates to which the pads are connected, are designed to begin conducting, or to undergo breakdown, thereby providing an electrical path to ground (or to the power-supply rail) when excess voltage occurs. Such protection devices are designed to avalanche (passing a large amount of current, and dissipating the energy of the incoming transient) before the voltage on the input pin can reach levels which would damage the gate oxide. Since the breakdown mechanism is designed to be nondestructive, the protective circuits provide a normally open path that closes only when the high voltage appears at the input or output terminals, harmlessly discharging the node to which it is connected.
However, technological advances are leading to the creation of smaller and faster components that are increasingly more fragile. The output stages of MOS circuits which, until now, have been capable of withstanding high discharge currents, are becoming more vulnerable. In particular, the advantages of the various techniques for improving the performance characteristics of integrated circuits are offset by increased sensitivity to over-voltages or discharges. Breakdown voltages of the junctions or punch-through voltages between drain and source of the MOS transistors are becoming lower and the gate oxide is more fragile. Such techniques as thinning of the gate oxide layers, the reduction in width of the conduction channels of the transistor or the very low doping and small thickness of the drain regions of transistors are forcing circuit designers to focus more attention to protection as transient voltages have a greater impact due to advances in IC fabrication. (Flow of large currents may lead to generation of hot carriers, which can become trapped in the gate oxide and produce a long-term shift in the characteristics of the device.)
A variety of device structures for protecting integrated circuits against electrostatic discharge have been proposed. See, e.g., Duvvury et al., "ESD: a pervasive reliability concern for IC technologies," 81 PRoc. IEEE 690 (1993); Amerasekera and Duvvury, ESD IN SILICON INTEGRATED CIRCUITS (1995); Ramaswamy et al., "EOS/ESD Reliability of Deep Sub-Micron NMOS Protection Devices", International Reliability Physics Symposium (IRPS) (1995). These publications, and the references cited therein, are incorporated by reference.